Guest Editorial: Special Section on Circuit and System Design Methodologies for Emerging Technologies

THE DEMAND for ever smaller, portable, energyefficient and high-performance electronic systems has been the primary driver for CMOS technology scaling. As CMOS scaling approaches physical limits, it has been fraught with challenges that required introduction of newer materials, manufacturing processes and device structures. High-κ oxide and metal-gate stack was introduced to mitigate oxide leakage which became a significant concern for sub-65nm CMOS technologies. Thin body, undoped channels, and multiple-gate structures were introduced to mitigate subthreshold leakage as battery life for mobile devices rose to prominence. 3D transistors such as doublegate FinFET and trigate transistors have been introduced to improve ON current and reduce subthreshold leakage without compromising layout efficiency that is crucial for device density which leads to lower costs. These innovations have allowed sustained scaling of CMOS technology which will continue to dominate semiconductor manufacturing for reasons that are both technological and financial. In CMOS technology, charge conveys logic information. Movement of charge is central to computation and storage, which entails a minimum energy dissipation of the order kB∗T per switching event. It has been argued that energy dissipation defines the fundamental limit of CMOS scaling. As an alternative to CMOS, a large variety of devices have been proposed for energy-efficiency and performance. Among them are carbon nanotube (CNT) field-effect transistors (CNT-FETs), graphene filed-effect transistors (GFETs), tunnel transistors, graphene nanoribbon tunnel field-effect transistors (GNR-TFET), quantum-dots, and single-electron devices (SET). At the same time newer memory technologies such as resistive random-accessmemory (RAM),memristors, Spin Transfer Torque Random Access Memory (STT-RAM) have shown promise to revolutionize the design landscape of electronic systems. However for these alternative technologies to become practical, design methodologies that allow efficient modeling, design space exploration, and trade-off analysis is crucial for the success of nanoelectronic circuit and system design. This is the driving motivation for this special section/issue of IEEE Transactions on Emerging Topics in Computing (TETC). For this special section, after an intensive peer-review process, a total of 4 papers have been selected. The paper titled ‘‘Scaling effects on static metrics and switching attributes of graphene nanoribbon FET for emerging technology’’ by Yaser M. Banadaki and Ashok Srivastava presents static metrics and switching attributes of GNR FETs for scaling of device the channel length up to 2.5nm. The article ‘‘Performance improvement in SC-MLGNRs interconnects using interlayer dielectric insertion’’ by Atul K. Nishad and Rohit Sharma discusses an analytical model for time domain analysis of side-contact multilayer graphene nanoribbons (SC-MLGNRs). The articles titled ‘‘Errors and power when communicating with spins’’ which is authored by Erol Gelenbe focuses on the analysis of error probabilities for bipolar spin based nano-communication between a set of interfering of nodes. The article titled ‘‘Powering up dark silicon: mitigating the limitation of power delivery via dynamic pin switching’’ by Shaoming Chen, et al. introduces techniques to power-up dark-silicon by dynamically switching a portion of I/O pins to power pins. These articles provide significant contributions to the state-of-art in nanoelectronic circuits and system design methodologies. This special issue/section well-serves the community of students and researchers in the field. The guest editors are indebted to the reviewers for the quality and timeliness of their reviews. The reviewers are experts in their fields and their feedbacks have enhanced the quality of the final submissions for this issue. We thank the authors for their patience, diligence and dedication at all stages of the review process. We are grateful to Dr. Fabrizio Lambardi, Editor-in-Chief (EiC), IEEE Transactions on Emerging Topics in Computing (TETC), for making this special section possible.